Dielectric layer structure

ABSTRACT

A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile film. The ILD layer further includes a low-k dielectric layer, and the single tensile film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/948,789, filed on Nov. 18, 2010, which is a division of U.S. patentapplication Ser. No. 11/834,643, filed on Aug. 6, 2007 and issued asU.S. Pat. No. 7,858,532 on Dec. 28, 2010, the entire disclosures ofwhich are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dielectric layer structure andmanufacturing method thereof, and more particularly, to a dielectriclayer structure having superior process control and stability andmanufacturing method thereof.

2. Description of the Prior Art

Devices in semiconductor industry need to undergo several complicatedprocesses such as photolithograph process, dry or wet etching process,ion implantation, and heat treatment, etc. to construct preciseintegrated circuits in layers. Among those complicated processes, theprocess control of dielectric layer etching has become a criticalfactor, particularly in some application such as damascene process orinterconnection technique. For example, in a damascene process, adielectric layer is etched to form patterns comprising trenches or via.Then the trenches or via are filled with copper, and a planarizationprocess is performed to complete formation of damascene structure.Additionally, to satisfy requirements of low RC delay effects, low-Kmaterial, ultra low-k (ULK) material, or porous low-k material is usedto be the dielectric layer in the damascene structure.

Please refer to FIGS. 1-5, which are schematic drawings of aconventional trench-first dual damascene process. As shown in FIG. 1, asubstrate 10 having at least a conductive layer 12 and a base layer 14comprising silicon nitride sequentially formed thereon is provided. Anda dielectric layer 16, a cap layer 18, a metal hard mask layer 20, and abottom anti-reflective coating (BARC) layer 22 are sequentially formedon the base layer 14. Then, a photoresist layer 30 is formed andpatterned to form an opening 32 by a well-known photolithography method.The opening 32 is used to define a trench pattern of a damascenestructure.

Please refer to FIGS. 1 and 2. Subsequently, an etching process isperformed. Accordingly a trench recess 34 is etched into the metal hardmask layer 20 and the cap layer 18 through the opening 32. The etchingis stopped on the cap layer 18. The remaining photoresist layer 30 andthe BARC layer 22 are then stripped off.

As shown in FIG. 3, another BARC layer 36 is deposited over thesubstrate 10 and fills the trench recess 34. And another photoresistlayer 40 is formed on the BARC layer 36. The photoresist layer 40 has anopening 42 patterned by a conventional photolithography method. Theopening 42 is situated directly above the trench recess 34 and theconductive layer 12, and is used to define a via pattern of a damascenestructure. As shown in FIG. 4, the BARC layer 36, the cap layer 18, andthe dielectric layer 16 are etched through the opening 42 with thephotoresist layer 40 being an etching mask. Thus, a partial via feature44 is formed in an upper portion of the dielectric layer 16. Then theremaining photoresist layer 40 and the BARC layer 36 are stripped off byan oxygen plasma.

Please refer to FIG. 5. Next, the metal hard mask layer 20 serves as anetching hard mask in an etching process, which is performed to etch awaythe cap layer 18 and the dielectric layer 16 through the trench recess34 and the partial via 44, thereby a dual damascene pattern comprising atrench opening 52 and a via opening 54 is obtained. Then, the damascenepattern is filled with a conductive metal such as copper followed by aplanarization process that is performed, thus a dual damascene structureis formed. It is noteworthy that the dielectric layer 16 possesses a lowmechanical strength and a compressive stress which leads to linedistortion occurring in the dielectric layer 16.

Furthermore, there is another phenomenon drawing attention in theconventional damascene formation process: Generally, the cap layer 18 isa silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) basedsilicon oxide layer with TEOS used as a precursor. Because the TEOSlayer comprises lots of Si—OH bonds and Si—H dangling bonds, the TEOSlayer is a hydrophilic layer which is apt to absorb moisture. And theabsorbed moisture is then desported from the TEOS layer and into thedielectric layer 16 in following process, thus Kelvin via open areformed in the dielectric layer 16. Kelvin via open reduces reliabilityof the process and influences electrical performance of the damasceneinterconnects formed following.

To solve the problem mentioned above, those skilled in the art providemany approaches, for example, a multi-layered cap layer such as atri-layered cap layer is provided. The tri-layered cap layer provides atensile stress layer offering a tensile stress which is opposite to thecompressive stress of the dielectric layer. The multi-layered cap layeralso provides hermetical layers sandwiching the tensile stress layer toprevent the tri-layered cap layer itself from absorbing the moisture andto prevent the dielectric layer from the desported moisture. However,due to the multi-layered characteristic, the process for themulti-layered cap layer has inferior process control, for example, it isnot easy to form openings or recesses in the multi-layered cap layer.And the multi-layered cap layer also has inferior process stability.Therefore, a simple layer capable of balancing stress in the dielectriclayer and preventing itself from absorbing moisture is needed.

SUMMARY OF THE INVENTION

Therefore the present invention provides a dielectric layer structureand a manufacturing method thereof to prevent line distortion and Kelvinvia open formation in dielectric layer.

According to the claimed invention, a dielectric layer structure isprovided. The dielectric layer structure includes an interlayerdielectric (ILD) layer covering at least a metal interconnect structureand a single tensile film. The ILD layer further includes a low-kdielectric layer, and the single tensile film is positioned on the low-kdielectric layer for counteracting at least a part of a stress of thelow-k dielectric layer.

According to the dielectric layer structure, the single tensile film isused to be a cap layer on the dielectric layer structure. Therefore atensile stress comparative to the stress of the dielectric layer isprovided to prevent line distortion in the dielectric layer. And ahydrophobic characteristic of the single tensile film prevents itselffrom moisture absorption, thus the Kelvin via open in the dielectriclayer resulted by water desorpted from the single tensile film infollowing processes is also avoided.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-5 are schematic drawings of a conventional trench-first dualdamascene process.

FIGS. 6-12 are schematic drawings illustrating a preferred embodiment ofthe method for manufacturing a dielectric layer structure.

DETAILED DESCRIPTION

Please refer to FIGS. 6-12, which are schematic drawings illustrating apreferred embodiment of the method for manufacturing a dielectric layerstructure according to the present invention. As shown in FIG. 6, asubstrate 100 is provided. The substrate 100 comprises a metal layer 102serving as a conductive layer and a base layer 104 comprising siliconnitride or SiCHN. Then a low-k dielectric layer 106 is sequentiallyformed thereon. The low-k dielectric layer 106 comprises porous low-kdielectric material or ultra low-K (ULK) material. A thickness of thelow-k dielectric layer 106 is about 800-5000 angstroms.

Please refer to FIG. 7. Next, a single tensile film 108 comprisingtetra-ethyl-ortho-silicate (TEOS) is formed on the low-k dielectriclayer 106 by a deposition process. The deposition process comprises aplasma-enhanced vapor deposition (PECVD) process, a sub-atmospherechemical vapor deposition (SACVD) process, or an atmosphere chemicalvapor deposition (APCVD) process. A high-frequency RF power and alow-frequency RF power of the deposition process can be adjusted tocontrol the tensile stress of the single tensile film 108 according tothe stress in the low-k dielectric layer 106. For example, when thehigh-frequency RF power is about 750-850 Watts and the low-frequency RFpower is about 100-200 Watts, the tensile stress of the single tensilefilm 108 is about 50-100 MPa. A thickness of the single tensile film 108is also adjustable according to the thickness of the low-k dielectriclayer 106. For example, when the thickness of the low-k dielectric layer106 is 800-5000 angstroms, the thickness of the single tensile film 108is about 200-1500 angstroms.

Silane (SiH₄), TEOS, tetra-methyl silane (4MS), tetra-methyl cyclotetra-siloxane (TMCTS), diethoxy-methyl-silane (DEMS) or othersilicon-containing chemicals can be added in the deposition processes asa precursor, and CO₂, N₂O, O₂, or O₃ can be added as an oxidizing agent.In addition, He, Ar, N₂, NH₃, CO₂, or O₂ can be used in the preferredembodiment for a pre-treatment or a post-treatment.

Please refer to FIG. 8. Then, a moisture preventing treatment isperformed to the single tensile film 108. The moisture preventingtreatment comprises an UV treatment, an electromagnetic treatment, or anN-plasma treatment. The moisture preventing treatment is used to alterthe polarity of the single tensile film 108 for enhancing moisturepreventing effect of the single tensile film 108. For example, the UVtreatment is performed with an UV light 110 having a wavelength of50-400 nanometers (nm) at a temperature of about 250-450° C. for 1-5minutes. In the UV treatment, the UV light 110 is used to break theSi—OH bonds and the Si—H dangling bonds in the single tensile film 108.Therefore the Si—OH bonds and the Si—H dangling bonds are eliminated andSi—O bonds or Si—Si bonds are formed. Thus the polarity of the singletensile film 108 is altered from hydrophilic into hydrophobic and asingle tensile hydrophobic film 112 is obtained as shown in FIG. 8.Moreover, the N-plasma treatment is performed with an N-containingplasma for nitrifying a surface of the single tensile film 108, and thusa hydrophobic surface 122 is obtained as shown in FIG. 9.

Please refer to FIG. 10. After performing the moisture preventingtreatment, a metal hard mask layer 130 comprising TiN is formed on thesingle tensile film 108. When forming the metal hard mask layer 130, thesubstrate 100 is placed in an nitrogen environment, then an N-plasma isintroduced to bombard a Ti metal target, thus the metal hard mask layer130 comprising TiN is formed. It is noteworthy that before bombardingthe Ti metal target, said N-plasma can be used in the N-plasmatreatment, therefore the hydrophobic surface 122 is obtained and thestep of forming the metal hard mask layer 130 can be performed in thesame apparatus. Thus it can be seen that the N-plasma treatment, whichis one approach of the moisture preventing treatment, and the step offorming the metal hard mask layer 130 can be performed in-situ. Ofcourse the moisture preventing treatment and the step of forming themetal hard mask layer 130 can be performed ex-situ. Furthermore, asshown in FIG. 10, the single tensile film 108 can be altered to be thesingle tensile hydrophobic film 112 with the UV treatment first, thenits surface can be treated to be the hydrophobic surface 122 with theN-plasma treatment, and the metal hard mask layer 130 can be formed inthe same apparatus.

Please refer to FIGS. 11-12. Then, a photoresist layer 140 is formed onthe metal hard mask layer 130. Additionally, a bottom anti-reflectivecoating (BARC) layer (not shown) can be formed on the metal hard masklayer 130. And a conventional photolithography method is performed topattern the photoresist 140, thus an opening 142 used to define apattern is formed as shown in FIG. 11. Please refer to FIG. 12, anetching process is performed to etch the metal hard mask layer 130 tothe single tensile hydrophobic film 112 through the opening 142 and toform an opening 144. A depth of the opening 144 is not limited as shownin FIG. 12 and is adjustable according to requirements of the process,even to penetrate the single tensile hydrophobic film 112.

According to the method for manufacturing dielectric layer structureprovided by the present invention, the compressive stress of the low-kdielectric layer 106 can be balanced by the tensile stress provided bythe single tensile film 108, therefore pattern or line distortion in thelow-k dielectric layer 106 due to the compressive stress is avoidedeffectively. And the single tensile film 108 which comprises hydrophilicTEOS is altered in to the single tensile hydrophobic film 112, even tofurther comprise the hydrophobic surface 122 by the moisture preventingtreatments, therefore the moisture absorption is effectively prevented.Thus problems of moisture absorption in the low-k dielectric layer 106from the single tensile film 108 and moisture desorption from the low-kdielectric layer 106 in following processes which causes Kelvin via openare fundamentally prevented. Additionally, when the low-k dielectriclayer 106 comprises porous low-k dielectric material or ULK materialwhich is more susceptible to the contaminant and damage, the singletensile film 108 provided by the present invention can prevent defectssuch Kelvin via open more effectively. Therefore process stability isimproved. What is noteworthy is that due to the single tensilehydrophobic film 112 comprising only one lamination, the entire processfurther benefits from simpler process control and superior processstability.

Please refer to FIGS. 8 and 9 again. As mentioned above, the presentinvention provides a dielectric layer structure comprising a low-kdielectric layer 106 and a single tensile hydrophobic film 112positioned on the low-k dielectric layer 106. The low-k dielectric layer106 comprises porous low-k dielectric material or ULK material. Athickness of the low-k dielectric layer 106 is about 800-5000 angstroms.

The single tensile hydrophobic film 112 comprises TEOS. A thickness ofthe single tensile hydrophobic film 112 can be adjusted according to thethickness of the low-k dielectric layer 106 therefore a range of thethickness of the single tensile hydrophobic film 112 is 200-5000angstroms. The single tensile hydrophobic film 112 possesses a tensilestress which is comparative to a compressive stress of the low-kdielectric layer 106. The single tensile hydrophobic film 112 cancomprise a nitrified surface serving as a hydrophobic surface 122.

According to the dielectric layer structure provided by the presentinvention, the compressive stress of the low-k dielectric layer 106 canbe balanced by the tensile stress provided by the single tensilehydrophobic film 112, therefore pattern or line distortion in the low-kdielectric layer 106 is avoided effectively. And since the singletensile hydrophobic film 112 has the hydrophobic feature, moisture willnot be absorbed, therefore the moisture absorption is effectivelyprevented. Thus problems of moisture absorption in the low-k dielectriclayer 106 from the single tensile film 108 and moisture desorption fromthe low-k dielectric layer 106 in following processes which causesKelvin via open are fundamentally prevented.

Additionally, the dielectric layer structure provided by the presentinvention further comprises a metal hard mask layer (shown in FIG. 10)positioned on the single tensile hydrophobic film 112 for definingpatterns and protecting the low-k dielectric layer 106.

As mentioned above, according to the dielectric layer structure and themethod manufacturing thereof, the single tensile hydrophobic film isused to balance a comparative stress of the former layer such as thedielectric layer, therefore pattern or line distortion in the dielectriclayer is prevented. And the hydrophobic characteristic of the singletensile hydrophobic film prevents itself from moisture absorption, thusthe Kelvin via open in the dielectric layer resulted by water desorptedfrom the tensile hydrophobic film in following processes is alsoavoided. In other words, the dielectric layer structure provided by thepresent invention not only effectively improves the process control andprocess stability of the entire process, but also improves the processresult.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A dielectric layer structure comprising: an interlayer dielectric(ILD) layer covering at least a metal interconnect structure, whereinthe ILD layer comprises a low-k dielectric layer; and a single tensilefilm positioned on the low-k dielectric layer for counteracting at leasta part of a stress of the low-k dielectric layer.
 2. The dielectriclayer structure of claim 1, wherein the low-k dielectric layer comprisesporous low-k dielectric material or ultra low-k (ULK) dielectricmaterial.
 3. The dielectric layer structure of claim 1, wherein thelow-k dielectric layer comprises a thickness of 800-5000 angstroms. 4.The dielectric layer structure of claim 3, wherein the single tensilefilm comprises a thickness of 200-1500 angstroms.
 5. The dielectriclayer structure of claim 1, wherein the single tensile film comprises ahydrophobic film.
 6. The dielectric layer structure of claim 1, whereinthe single tensile film comprises tetra-ethyl-ortho-silicate (TEOS). 7.The dielectric layer structure of claim 1, wherein the single tensilefilm further comprises a nitrified surface.
 8. The dielectric layerstructure of claim 1 further comprises a hard mask layer positioned onthe single tensile film.
 9. The dielectric layer structure of claim 8,wherein the metal hard mask, the single tensile film and the ILD layerfurther comprise at least an opening for exposing the metal interconnectstructure.